Accelerating the Development of Hardware Accelerators

ASC [1], A Stream Compiler, is designed to enable rapid development of hardware accelerators while still producing results that match hand-crafted equivalents. An ASC program represents a dataflow system which can be seen as a stream; to avoid the difficulties often associated with behavioural synthesis, ASC allows direct implementation of a hardware design based on the programmer’s input. Stream architectures are constructed using a C++ based object oriented approach, and as shown in Figure 1, a single ASC description can target Field Programmable Gate Arrays (FPGAs) and also other accelerator platforms, such as Graphics Processing Units (GPUs) and Sony Playstation 2 vector units. Architectural differences are transparent to the programmer in a basic implementation, requiring only the selection of an appropriate target architecture. FPGAs show excellent potential as hardware accelerators for a wide class of applications. While running many times slower than modern Pentium-type processors, the massive fine-grained parallelism and many independent memory buses of FPGAs can permit order-of-magnitude speed-ups over software. However, programming FPGAs remains essentially a hardware design task and is much harder than writing software. High level synthesis tools attempt to bridge the gap between algorithm and implementation, however the circuits that are obtained usually compare poorly with handcrafted implementations. While intended for graphics acceleration, modern GPUs are highly programmable parallel stream computation engines [4] and increasingly suitable for general computation [3]. The Sony Playstation 2 processor contains two programmable vector units that can execute independently, the ability of this system to accelerate applications is thus indicative of the potential of upcoming similar architectures such as Cell. Through targeting multiple different acceleration architectures from a common description, we can compare the performance of each architecture for a particular algorithm. Once the best accelerator architecture has been selected, architecture specific extensions can be used to further optimise the implementation. Developer access to multiple levels in the design hierarchy offers the ASC programmer great flexibility of implementation when required, permitting optimisation at the alGPU PS2 ASC GPU ASC ASC PS2